1. Field of the Invention
The present invention generally relates to a method for fabricating an integrated circuit (IC), and more particularly to a method for fabricating a read only memory (ROM).
2. Description of the Related Art
Electrically erasable programmable read only memory (EEPROM) is a widely used device in personal computing equipment. As the name implies, an EEPROM can be erased and reprogrammed electrically without the need for ultraviolet illumination. The EEPROM utilizes a variant of the floating-gate metal oxide semiconductor field effect transistor (MOSFET). Data programmed into the EEPROM will not be lost after the power is turned off. However, the access speed (about 150.about.200 ns) of the EEPROM is relatively slow, because of larger area required. Recently, a flash memory was developed with a faster access speed of about 70.about.80 ns to overcome this problem.
A conventional flash memory can be characterized by a two-layer structure comprising a floating gate and a control gate. The floating gate made of polysilicon to store charges is normally in the "floating" state without connecting to any circuitry. On the other hand, the control gate situated on the floating gate to control data access is generally electrically connected to a word line. The above-mentioned two-layer structure comprising the floating gate and the control gate is generally referred to as a stacked gate.
The circuitry layout of a conventional flash memory is shown in FIG. 1, which depicts a portion of a flash memory array. As shown in FIG. 1, the control gate of each flash memory in the same row is electrically connected to the same word line. For example, control gate G of a flash memory 100 is electrically connected to a word line WL2, while a word line WL1 is electrically connected to control gates of another row of flash memories. Sources of the flash memories in the same column are electrically connected to the same bit line. For example, source S of the flash memory 100 is electrically connected to a bit line BL1. Similarly, drains of the flash memories in the same column are electrically connected to another bit line. For example, drain D of the flash memory 100 is electrically connected to a bit line BL2. Note that bit lines electrically connected to sources and drains of a flash memory are different. Generally, the bit lines BL1, BL2, and BL3 are vertically distributed and the word lines WL1 and WL2 are horizontally distributed to jointly form the flash memory array.
FIG. 2 shows a structure layout of a conventional flash memory array. FIGS. 3A through 3C are cross sectional views taken along the line I--I from FIG. 2 showing the processing steps for fabricating a conventional flash memory. FIGS. 4A and 4B are cross sectional views taken along the line II--II from FIG. 2 showing the processing steps for fabricating a conventional flash memory.
Refer first to FIGS. 3A and 4A, in which a substrate 10 is provided, on which a pad oxide layer (not shown) is formed by thermal oxidation. Subsequently, a field oxide layer 14 is formed on the substrate 10 by local oxidation to define an active area. The pad oxide layer is then removed by using a wet etching method. A tunneling oxide layer 12 having a thickness of about 100 .ANG. is formed on the surface of the active area by thermal oxidation. Subsequently, a polysilicon layer having a thickness of about 1500 .ANG. is deposited on the tunneling oxide layer 12 by low pressure chemical vapor deposition (LPCVD). By using photolithography and etching technologies, the polysilicon layer is patterned to form a polysilicon layer 16, which is used as the floating gate of the flash memory.
An inter-poly dielectric layer is deposited by LPCVD covering the polysilicon layer 16. The inter-poly dielectric layer is a three-layer structure made of oxide/nitride/oxide (ONO), and has a thickness of about 250 .ANG.. Subsequently, a polysilicon layer having a thickness of about 3000 .ANG. is deposited on the inter-poly dielectric layer by LPCVD. The polysilicon layer and the inter-poly dielectric layer are then patterned to form a polysilicon layer 20 and an inter-poly dielectric layer 18, respectively, by using the photolithography and etching technologies.
Ions with a higher concentration are subsequently implanted into the substrate 10 to form a doped region 22 by using the polysilicon layer 20 as a mask. To this end, the polysilicon layer 20, the inter-poly dielectric layer 16, and the tunneling oxide layer 12 jointly form a gate electrode of the flash memory transistor.
A mask (not shown) is used to cover portions of the substrate 10 exposing one of the doped regions 22 at one side of the gate electrode. A dopant is implanted in an oblique angle into the substrate 10 by ion implantation. Subsequently, an annealing process is performed to form a tunneling diffusion region 24. The tunneling diffusion region 24 surrounds the doped region 22 and extends to a region below the gate electrode. When the tunneling diffusion region 24 is formed, the mask is removed.
Refer to FIG. 3B, in which an oxide layer is deposited covering the substrate 10 by LPCVD. Subsequently, a spacer 26 is formed on each side of the gate electrode by using an etching back process. The spacer 26 and the gate electrode are used as a mask so that a dopant can be implanted into the substrate 10 by ion implantation to form a doped region 28 as shown in FIG. 3B. At this time, the cross sectional views taken along the line II--II from FIG. 2 is as shown in FIG. 4A.
Refer to FIGS. 3C and 4B, in which a dielectric layer 30 is deposited by LPCVD covering the substrate 10. A contact window 32 is formed in the dielectric layer 30 by using the photolithography and etching processes to expose the doped region 22. A metal layer 34 is deposited on the substrate, filling the contact window 32 to electrically connect to the doped region 22. The metal layer 34 is used as a bit line. Subsequent processes to fabricate the flash memory are well known by those who skilled in the art and are therefore not described herein.
Data can be stored in transistors of the conventional flash memory by using hot electrons and erased by using the Fowler-Nordheim tunneling effect. That is, when data is to be stored on the floating-gate transistor, a large voltage (about 5.about.6 volts) are applied between the drain and source of the transistor. A large voltage is also applied to the control gate of the transistor, so that the hot electrons flowing out from the source can pass through the tunneling oxide layer near the drain end and trapped within the floating gate layer. The threshold voltage at the floating gate is increased, which implies data is stored. To erase the data stored in the transistor, a positive voltage is applied to the source while a negative voltage is applied to the control gate, so that the trapped electrons within the floating gate are returned to the substrate through the tunneling oxide layer. The floating gate resumes to the state before data is stored.
When integrated circuits demand a higher integration, the channel length under the gate electrode needs to be shorter to increase the operating speed. Unfortunately, the channel length can not be shortened without a limit. Conventional fabricating methods to shorten the channel length depend on alignment technologies during the photolithography process, which imposes constraints to further shorten the channel length and therefore the size of the device.
On the other hand, if the channel length can not be shortened, the doping concentration needs to be higher, which results in a leakage current at the drain or even an electrical breakdown, because of the hot electrons effect. Furthermore, the electrons entering the floating gate from the source will make the programming, reading, and erasing processes out of control.